A Serializer/Deserializer (SerDes) is an integrated circuit transceiver that facilitates that transmission of parallel data between two points over serial streams. A SerDes includes a transmitter section that converts parallel data to serial data, and a receiver section that converts serial data to parallel data.
In a SerDes link, it can be desirable to know the margin of the link before the link will degrade (that is it starts to have a significant number of errors). It is important to monitor the margin of SerDes links to ensure that the bit error rate (BER) is low enough for a particular application.
One approach is to monitor the receive signal at the integrated circuit (IC) pins. However, such monitoring can be very misleading due to package effects, and internal processing (i.e. equalization) within the IC. Moreover, it can be difficult to access the IC pins without distorting the receive signal.
Typically, most SerDes standards target a 10-12 BER (that is at most a single bit error within one Tera-bit of data), and some standards are calling for a BER of 10-15 (that is at most a single bit error within one Peta-bit of data).
Having a method to show the margins of a link gives a better sense that the link is performing to specification, as test times can be very long. Such methods can also be used to track down problems (worse than expected bit error rate, one link out of many having a worse BER than the others, etc).
There are several known methods available to determine the margin of a SerDes link. Metallic loop-back involves taking the receive (Rx) signal and sending it back out the transmit (Tx) port of the integrated circuit without doing any clock recovery. This allows one to see the data at the Rx pins without distorting the signal (but it does add “jitter” and “noise” due to the analog stages in the Tx path); however one has to have a separate Tx port available or no longer have a “normal” link (as the Tx side is not working normally). Given this data, one can process it off-line to get the confidence that the Rx side of the link will work correctly.
Another known method available to determine the margin of a SerDes link is to generate internal eye diagram plots, which are pictures of what the eye diagram looks like within the integrated circuit. These can be presented as either statistical eye plots or trajectory plots and typically requires either an extra Rx path or can only be used in a “test” mode.
A still other known method available to determine the margin of a SerDes link is to use bit error rate (BER) checkers when the SerDes link is in a “test” mode. This involves sending known patterns (for example PRBS-31) from the transmitter to the receiver of the SerDes and having a BER monitor on chip indicate the number of errors. This requires the chip to be in a “test” mode.
Most communication protocols have some capabilities for monitoring performance of a communication link such as cyclic redundancy check (CRC) or binary interface parity (BIP) but their usefulness vary greatly. Mostly, these methods just state that 1 or more errors have happened in the last frame/packet and there is a need to either drop the frame/packet or ask it to be resent. These methods do not give the real number of bit errors, thus making it difficult to estimate margins.
Current SerDes receivers have built in capabilities to monitor the margins in a SerDes link to ensure that the link is performing to specification. These methods include receiving the data at the slicer output and offsetting the slicer level in order to assess the amplitude margin of the link. Another method involves receiving the data at the slicer output and offsetting the sampling time of the slicer in order to determine the timing margin of the link. A third method involves receiving the data at the slicer output and adding a current/voltage to input signal of the slicer in order to assess the amplitude margin of the link. In all of these methods the bit-error rate at the output of the SerDes receiver is measured in order to assess the margin, and they all require that the SerDes link is operating in a special test mode.
Some drawbacks to the current methods for monitoring the margins in a SerDes link include: they require the SerDes to be operating in a special test mode; or they require a full second receiver path in addition to the existing receive data path so as to not disrupt the normal operation of the SerDes link. Furthermore, some of the current methods mentioned above also require a special repeating test data stream to be sent to the receiver.
It is, therefore, desirable to provide an improved method for assessing the performance of a SerDes link.